Electronic systems often require the ability to store data to a memory (writing) and retrieve data from the memory (reading). A memory array is composed of memory cells. Each memory cell is capable of storing a bit of data. Such memory cells are typically composed of transistors such as MOSFET.
Scaling of transistor dimensions and of electronic devices in the microelectronics industry has brought about two unintended significant problems related to memory cells: the first is a rapid increase in susceptibility to radiation-induced errors; the second is a rise of overall power consumption, mainly due to the increase of leakage currents.
Radiation induced errors in electronic circuits are caused by an energy transfer when a radiation particle strikes the substrate of the electronic circuit, resulting in the excitement of electron-hole pairs. If the impact occurs at a transistor's reversed biased drain junction, these electrical charge carriers will drift into the junction, resulting in a transient current pulse. Due to the finite resistance of the transistors composing the memory cell, this current pulse may result in a voltage level change of the struck junction, logically interpreted as a change of the data stored in the cell.
Low voltage operation as a manner of power consumption reduction only aggravates radiation susceptibility related reliability issues, since the electrical charge accumulating in the struck junction depends on the junction's capacitance and voltage.
Either low power adequate memory cells or radiation-hardened memory cells have been designed before, but there is a need for a memory cell which efficiently combines low power and SEU tolerance characteristics.